A digital electronic circuit is typically tested by successively launching each of a set of test vectors into the inputs(s) of the circuit and then monitoring the output response following receipt of each test vector. In practice, the test vectors are generated by an automatic test pattern generator which typically takes the form of a computer program executed by a conventional digital computer. Present-day automatic test pattern generators fix the maximum amount of effort (i.e., time) to be spent during a test generation cycle for generating a test (i.e., one or more test vectors) for each fault regardless of the fault difficulty. This often leads to inefficiency because allocating too large a maximum test vector generation effort will cause the test pattern generator to spend too much time attempting to generate a test for a fault that is too difficult to test. On the other hand, if the maximum allocated generation effort is too small, then a fault may go undetected because not enough effort was spent to generate a test for successfully detecting the fault, resulting in inadequate fault coverage.
Thus, there is a need for a method for speeding up the generation of test vectors to increase overall efficiency of the test vector generation process.